The present invention generally relates to the field of magnetic memories. More particularly, the present invention relates to a write pulse generator device and method for a magnetic memory wherein the write pulse generator is coupled to a conductor which crosses the memory cell and is configured to provide a discharge current to the conductor during a write operation of the memory cell to improve the write performance of the magnetic memory.
Magnetic random access memory (MRAM) is a type of non-volatile magnetic memory which includes magnetic memory cells. A typical magnetic memory cell includes a layer of magnetic film in which the magnetization of the magnetic film is alterable and a layer of magnetic film in which magnetization is fixed or xe2x80x9cpinnedxe2x80x9d in a particular direction. The magnetic film having alterable magnetization is typically referred to as a data storage layer, and the magnetic film which is pinned is typically referred to as a reference layer.
A magnetic memory cell is usually written to a desired logic state by applying external magnetic fields that rotate the orientation of magnetization in its data storage layer. The logic state of a magnetic memory cell is indicated by its resistance which depends on the relative orientations of magnetization in its data storage and reference layers. The magnetization orientation of the magnetic memory cell assumes one of two stable orientations at any given time. These two stable orientations, parallel and anti-parallel, represent, for example, logic values of xe2x80x9c0xe2x80x9d and xe2x80x9c1.xe2x80x9d
Typically, the orientation of magnetization in the data storage layer aligns along an axis of the data storage layer that is commonly referred to as its easy axis. The external magnetic fields are applied to flip the orientation of magnetization in the data storage layer along its easy axis to either a parallel or anti-parallel orientation. With parallel orientation, the magnetic memory cell is in a low resistance state because the orientation of magnetization in its data storage layer is substantially parallel along the easy axis. With anti-parallel orientation, the magnetic memory cell is in a high resistance state because the orientation of magnetization in its data storage layer is substantially anti-parallel along the easy axis.
A typical magnetic memory includes an array of magnetic memory cells. Word lines extend along rows of the magnetic memory cells, and bit lines extend along columns of the magnetic memory cells. Each magnetic memory cell is located at an intersection of a word line and a bit line. A selected magnetic memory cell is usually written by applying electrical currents to the particular word and bit lines that intersect at the selected magnetic memory cell. The electrical current applied to the particular bit line generates a magnetic field substantially aligned along the easy axis of the selected magnetic memory cell. This magnetic field may be referred to as a bit line write field. An electrical current applied to the particular word line also generates a magnetic field substantially perpendicular to the easy axis of the selected magnetic memory cell. This magnetic field may be referred to as a word line write field. The sum of the bit line write field and the word line write field must be greater than a write threshold to enable the magnetization in the data storage layer to change and align according to the applied write fields. A magnetic memory cell receiving only the word line or the bit line write field is termed a xe2x80x9chalf-selectedxe2x80x9d magnetic memory cell. The magnitudes of the word line and bit line write fields are usually chosen to be high enough so that the magnetization in the data storage layer of the selected magnetic memory cell changes and aligns according to the applied write fields, but not too high so that the half-selected magnetic memory cells which are subject to either the word line or the bit line write field do not change their direction of magnetization in the data storage layer.
Data is typically written to the MRAM array as n-bit words. For example, a 16-bit word might be written to sixteen memory cells by supplying a write current to a word line crossing the sixteen memory cells and supplying separate write currents to the sixteen bit lines crossing the sixteen memory cells. Peak currents can be especially high for highly parallel modes of operation, such as for 64-bit wide or 128-bit wide operations. With these modes, data can be written to 64 or 128 memory cells by supplying a single word line current and 64 or 128 separate bit line currents to each of the bit lines crossing the magnetic memory cells.
One problem that can occur during the highly parallel modes of operation is high peak write currents. High peak write currents can create unacceptable levels of current noise which can degrade the write performance of the MRAM arrays. High peak write currents also can reduce reliability as a result of electromigration occurring in the metal interconnect layers which route read and write control circuitry to the memory cell array.
Another problem that can occur is difficulty in controlling the write currents to a specified range to write the individual magnetic memory cells in the array. A selected magnetic memory cell receives both the word line and the bit line write fields. With high peak write currents, it can become more difficult to control the write currents to a level high enough to write the selected magnetic memory cell but not so high that half-select switching occurs.
Manufacturing variation among the magnetic memory cells can also increase the difficulty in controlling the write currents to a specified range. For example, manufacturing variation in the dimensions or shapes of the magnetic memory cells may increase the likelihood of half-select switching. Furthermore, variation in the thicknesses or in the crystalline anisotropy of the data storage layers of the magnetic memory cell may also increase the likelihood of half-select switching.
The present invention is a write pulse generator device and method for a magnetic memory. The magnetic memory includes a memory cell and a conductor wherein the conductor crosses the memory cell. The write pulse generator is coupled to the conductor and is configured to provide a discharge current to the conductor during a write operation of the memory cell.